The memory cells of dynamic random access memories (DRAMs) are comprised of two main components, a field-effect transistor (FET) and a capacitor which functions as a storage element. The need to increase the storage capability of semiconductor memory devices has led to the development of very large scale integrated (VLSI) cells which provides a substantial increase in component density. As component density has increased, cell capacitance has had to be decreased because of the need to maintain isolation between adjacent devices in the memory array. However reduction in memory cell capacitance reduces the electrical signal output from the memory cells, making detection of the memory cell output signal more difficult. Thus, as the density of DRAM's increases, it becomes more and more difficult to obtain reasonable storage capacity.
In order to meet the high density requirements of very large scale integrated cells in DRAM cells, some manufacturers are utilizing DRAM memory cell designs based on non-planar capacitor structures, such as complicated stacked capacitor structures and deep trench capacitor structures. Although non-planar capacitor structures provide increased cell capacitance, such arrangements create other problems that effect performance of the memory cell. For example, trench capacitors are fabricated in trenches formed in the semiconductor substrate, the problem of trench-to-trench charge leakage caused by the parasitic transistor effect between adjacent trenches is enhanced. Moreover, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate which functions as one of the storage plates of the trench capacitor. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a soft error.
Another technique that has been used, commonly referred to as the three-transistor cell, uses transistors for gain input multipliers driving the output data or bit line. The transistors function as simple voltage amplifiers. A significant shortcoming of this arrangement is the requirement for additional lines to the memory cell, which is a serious disadvantage, particularly in high density memory structures.
Another approach has been to provide DRAM cells with dynamic gain, commonly referred to as gain cells. For example, U.S. Pat. No. 5,220,530 discloses a two-transistor gain-type dynamic random access memory cell. The memory cell includes two field-effect transistors, one of the transistors functioning as write transistor and the other transistor functioning as a data storage transistor. The storage transistor is capacitively coupled via an insulating layer to the word line to receive substrate biasing by capacitive from the read word line. This gain cell arrangement requires two write lines and a separate read line.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a dynamic random access memory cell which is characterized by an output signal of increased amplitude which is easier to detect.